The present invention relates to a semiconductor memory device which performs a read/write operation in a pipeline system in synchronism with a clock signal, and to a technology effective for application to, for example, a synchronous DRAM (Dynamic Random Access Memory) or a double data rate synchronous DRAM or the like.
With a rapid increase in operating frequency of a processor, there has also recently been a growing demand for the speeding up of a data transmission rate as well as the shortening of an access time as a demand for a DRAM. A synchronous DRAM operated in synchronism with a clock signal (hereinafter abbreviated as xe2x80x9cclockxe2x80x9d) has been developed with its demand. A DDR (Double Data Rate) type synchronous DRAM or the like for performing the input/output of data on the rising and falling edges of the clock has been proposed to achieve its further speeding up, which is becoming mainstream therefor.
The double data rate synchronous DRAM having such a configuration has been disclosed in 1999 ISSCC Digest of Technical Papers, p.412-p.413 (1999 IEEE Internal Solid-State Circuit Conference WP24.2 xe2x80x9cA 2.5 V 333Mb/s/pin 1 Gb Double Date Rate SDRAMxe2x80x9d, p.412-p.413).
Unexamined Patent Publication No. Hei 10-504129 (corresponding U.S. Pat. No. 5,544,124) discloses an optimizing circuit for a synchronous memory device having a programmable latency time. Unexamined Patent Publication No. Hei 10-162572 discloses a data transmission system capable of coping with various latency demands. Unexamined Paten Publication No. Hei 11-224486 (corresponding U.S. Pat. No. 6,151,270) discloses a synchronous memory device which controls activating/non-activating times of a column select signal according to a value corresponding to a CAS latency during a read operation. Unexamined Patent Publication No. Hei 11-66848 discloses a semiconductor memory device capable of operation with a sufficient margin of cycle time.
FIG. 29 shows a configuration of a double data rate synchronous DRAM discussed by the present inventors, FIG. 30 shows a timing chart at its read operation, and FIG. 31 shows a timing chart at its write operation, respectively. The following problems discussed by the present inventors and the analysis of causes of the problems are part of the present invention.
The semiconductor memory device shown in FIG. 29 comprises a memory cell array 123, an address buffer 101 which latches an address inputted from outside, an address register 103 which latches the address captured by the address buffer 101, a row address decoder 109 which decodes a row address to thereby select a word line, a column address decoder 116 which decodes a column address to thereby select at least one bit line, a row address latch 104 which transmits a row address to the row address decoder 109 in response to the output of the address buffer 101, a column address counter 111 which changes a column address thereinside, a column address latch 110 which transmits a column address to the column address counter 111 in response to the output of the address buffer 101, a command decoder 102 which generates internal control signals in response to control signals supplied from outside, an output buffer 120 which outputs data read from the memory cell array 123 to the outside, an output clock generator 119 which controls timing for data outputted from the output buffer 120, an input buffer 121 which receives data inputted from the outside, a read/write circuit 117 which transmits data read from the memory cell array 123 to the output buffer 120 or writing data inputted from the input buffer 121 into the memory cell array 123, etc. One feature of the synchronous DRAM resides in that a CAS latency (corresponding to the number of clock cycles set from the capturing of a column address to the output of read data) can be set based on command codes (hereinafter called simply xe2x80x9ccommandsxe2x80x9d).
A read operation of data by the DRAM shown in FIG. 29 will be explained with reference to FIG. 30. FIG. 30 is a timing chart at the time that the number of clock cycles (tRCD) set from an ACTV command for providing instructions for the start of operation to a READ command or a WRITE command (called a column command where both commands are distinguished from each other) for providing read or write instructions is 2 cycles and a CAS latency is 2 cycles. As shown in FIG. 30, a row address is taken in from the address buffer 101 simultaneously with the time when an ACTV command is inputted. In response to the ACTV command, the row address is latched into the address register 103 according to ACLK outputted from a command decoder 102. Further, the row address is latched into the row address latch 104 according to a clock RCLK outputted from the command decoder 102 in response to the ACTV command. Afterwards, the rod decoder 109 decodes the row address signal to thereby select a word line corresponding to the value of the row address. When the corresponding word line is selected, data is outputted from a memory cell connected to the selected word line to at least one bit line. When the data is fully outputted to the bit line, a sense amplifier is started up so that the potential on the bit line is amplified.
A READ command is inputted after the elapse of two cycles since the entry of the ACTV command. Simultaneously with it, a column address is taken in from the address buffer 101. In response to the READ command, the column address is latched into the address register 103 according to a clock ACLK outputted from the command decoder 102. Further, the column address is latched into the column address latch 110 according to a clock YCLK1 outputted from the command decoder 102 in response to the READ command. Afterwards, the column address signal passes through the column address counter 111 and is decoded by the column decoder 116 to thereby select at least one bit line corresponding to the value of the column address. At this time, a bit-line selectable condition is that the potential on at least one bit line has fully been amplified. After the selection of the bit line, data on the bit line passes through the read circuit 117 and is outputted to the outside through the output buffer 120. At this time, the timing provided to output read data to the outside through the output buffer 120 is determined according to QCLK1 generated from the output clock generator 119. In the double data rate synchronous DRAM, 2n-bit data equivalent to twice the number of output bits (n) are read from the read circuit 117 to the output buffer 120, and the data are outputted by n bits in synchronism with the rising and falling edges of the clock. Incidentally, a column decoder input and a column select signal are shown in FIG. 30 two by two because continuous addresses are generated from the column address counter 111 in a burst mode or the like and the read operation is carried out based on the same addresses.
FIG. 31 shows a timing chart at a data writing of the DRAM shown in FIG. 29 where tRCD is 2 cycles and a CAS latency is 1 cycle. As shown in FIG. 31, a row address is taken in simultaneously with the entry of an ACTV command upon writing. The row address is decoded by the row decoder 109 to select a word line. Data stored in a memory cell is outputted to at least one bit line. When the bit line is fully set up, a sense amplifier is started up to amplify the potential on the bit line.
A WRITE command is inputted after the elapse of 2 cycles since the entry of the ACTV command. Simultaneously with the entry of the WRITE command, a column address is taken in. Afterwards, the column address is decoded in a manner similar to the reading to thereby select at least one bit line. Write data is captured from outside in 1 cycle=(CAS latencyxe2x88x921) since the entry of the WRITE command. In the double data rate synchronous DRAM at this time, n-bit write data are respectively taken in by the input buffer 121 on both the rising and falling edges of the clock and sent to the memory cell array 123 through the write circuit 117 as 2n bits, followed by writing into the corresponding memory cell through the selected at least one bit line.
The double data rate synchronous DRAM has an advantage in that the output of the read data and the capturing of the write data are carried out on both the rising and falling edges of the clock, a data transmission rate is improved. However, the double data rate synchronous DRAM is accompanied by a problem that since one cycle is made blank between the input of the ACTV command and the input of the column command as shown in FIGS. 30 and 31 as to the commands, the efficiency of transfer of each command is low and a CPU outputs the column command after having waited for one cycle after the output of the ACTV command, whereby the performance of the entire system is not sufficiently enlarged.
Therefore, a discussion has been made of a synchronous DRAM of such a type that the timing provided to input a column command inputted after the entry of the ACTV command is inputted in a once-cycle advanced state. An advantage is obtained in that since the CPU is capable of making a transition to another process early by one cycle because the entry timing of the column command is advanced by one cycle, the performance of the overall system is improved. In this case, however, the support for various systems can be achieved by varying the advanced latency.
However, it has been found that the double data rate synchronous DRAM or the like having such a configuration as shown in FIG. 29 is not able to realize or implement such an advanced entry of column command. Described specifically, when the READ command is inputted in advanced manner, the column address is also inputted in advanced manner, so that at least one bit line is selected before the amplification of data on the bit line by the sense amplifier. As a result, correct data is not read out. Further, the bit line is selected before the input of correct write data into the write circuit due to the advanced entry of the WRITE command, so that no correct data is written therein.
An object of the present invention is to provide a clock synchronous type semiconductor memory device capable of reading and writing correct data even when a read command and a write command are inputted in advanced manner and a column address is inputted in advanced manner.
Another object of the present invention is to provide a clock synchronous type semiconductor memory device capable of shortening a cycle time and thereby speeding up a data transmission rate.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application are as follows:
In order to achieve the above objects, there is provided a semiconductor memory device according to the present invention, wherein in a semiconductor memory like a double data rate synchronous DRAM, a register capable of setting a value (advanced latency) for specifying an entry cycle of a read or write command is provided, and a timing adjustment register for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system between a column address latch circuit and a column decoder.
Namely, there is provided a semiconductor memory device comprising a memory cell array having a plurality of word lines and a plurality of bit lines to which memory cells are connected, a row address latch circuit which latches a row address inputted from outside, a row decoder which decodes the row address to thereby select a word line lying within the memory cell array, a column address latch circuit which latches a column address inputted from outside, a column decoder which decodes the column address to thereby select at least one bit line lying within the memory cell array, an output buffer which outputs data read from the memory cell array, an input buffer which captures input data, and a first register capable of setting values for specifying a timing provided to take the data in the input buffer and a timing provided to output the data from the output buffer. Further, the semiconductor memory device wherein the input buffer and the output buffer are configured so as to determine their operating timings according to the values set to the first register, is provided with a second register capable of setting a value for specifying a timing provided to input a data read command or a data write command, and a timing adjustment circuit provided on a column address signal path between the column address latch circuit and the column decoder and for delaying a signal by a predetermined time according to the value set to the second register.
According to the above means, since the timing adjustment circuit is capable of controlling a propagation delay time for a column address signal according to the value (the value of column command advanced latency) set to the second register, the selection of at least one bit line by the column address decoder can be carried out in accordance with timing provided to amplify the potential on the bit line even where the column address is captured in advanced manner due to the advanced entry of the read command or the write command (column command), and hence correct data can be read out. Further, since the corresponding bit line is selected after the write data has been captured by the input buffer, correct data can be written into a memory cell connected to the selected word line.
Even if each value (CAS latency) set to the first register is changed, the value (the value of column command advanced latency) set to the second register is independently set. Thus, since the timing adjustment circuit is also controlled independently, the proper operation is assured. Further, even when the value (CAS latency) set to the first register remains uncharged and the value (the value of column command advanced latency) set to the second register is changed, the propagation delay time for the column address signal is adjusted by the timing adjustment circuit controlled independently of the set value (CAS latency) of the first register. Further, since the corresponding bit line can be selected in accordance with the timing provided to amplify the potential on the bit line and the timing provided to input the write data, the proper operation is assured.
Preferably, the semiconductor memory device is provided with a circuit which generates an internal control signal used to control each internal circuit, based on a control signal supplied from outside, and a delay control circuit for delaying the internal control signal by a predetermined cycle time according to the value set to the second register. Further, the timing adjustment circuit is controlled by the internal control signal adjusted by the delay control circuit so as to make a timing adjustment to a column address signal. Thus, each signal for controlling the timing control circuit can be generated with satisfactory efficiency systematically.
Further, preferably, the semiconductor memory device is provided with a circuit which generates a signal for supplying a timing provided to operate the output buffer, based on the internal control signal. Further, the circuit is controlled by the internal control signal generated by the delay control circuit and is configured so as to be capable of delaying a signal generated according to the value set to the second register. Thus, the timing adjustment circuit and the circuit for generating the signal for supplying the timing provided to operate the output buffer can be controlled by a common signal, and hence the configuration of the control circuit can be simplified.
Incidentally, the position to place the timing adjustment circuit may be any location so long as the timing adjustment circuit is placed between the column address latch circuit and the column decoder. It is however desirable that when a column address counter for automatically updating the column address latched into the column address latch circuit is provided, the timing adjustment circuit is provided on the column address signal path between the column address counter and the column decoder or between the column address latch circuit and the column address counter. Thus, in the semiconductor memory device operated in synchronism with the clock, the operation of performing address latch and address updating, and the operation of decoding the column address are executed distributedly over other cycles to thereby allow the shortening of a cycle time.
When the semiconductor memory device is further provided with a plurality of spare memory arrays capable of being substituted for normal memory arrays in the memory cell array, a relief address storage circuit capable of storing addresses lying in a memory array having a defect, an address comparator which compares an input column address and each of the addresses stored in the relief address storage circuit, and a redundant column decoder which decodes a signal based on the result of comparison by the address comparator to thereby select any of the spare memory arrays, the column address comparator may be configured so as to compare an address outputted from the column address counter and each address stored in the relief address storage circuit, and a second timing adjustment circuit may be provided on a signal path between the address comparator and the redundant column decoder. Providing the second timing adjustment circuit makes it possible to more optimally control the timing provided to transmit a column address signal. In the semiconductor memory device operated in synchronism with the timing clock, the operation of performing address latch and address updating, the operation of performing an address comparison, and the operation of decoding the column address are executed distributedly over other cycles to thereby allow the shortening of a cycle time.
Further, when a column predecoder for predecoding the column address is provided in a stage preceding the column decoder, the timing adjustment circuit is provided between the column address counter and the column predecoder, and the second timing adjustment circuit is provided between the column address comparator and the column predecoder, respectively. The number of the timing adjustment circuits increases as they approach the column decoder. Owing to such a configuration, however, a cycle time can be shortened without an increase in circuit scale of each timing adjustment circuit.
However, when the column predecoder for predecoding the column address is provided in the stage preceding the column decoder, the timing adjustment circuit may be provided between the column predecoder and the column decoder, and the second timing adjustment circuit may be provided between the column address comparator and the column decoder, respectively. Since the timing adjustment circuit becomes easy to make the optimum operation distribution as it approaches the column decoder, a cycle time can further be shortened owing to such a configuration although a circuit scale slightly increases.
In addition, when the semiconductor memory device is further provided with a plurality of spare memory arrays capable of being substituted for normal memory arrays in the memory cell array, a relief address storage circuit capable of storing addresses lying in a memory array having a defect, an address comparator which compares an input column address and each of the addresses stored in the relief address storage circuit, and a redundant column decoder which decodes a signal based on the result of comparison by the address comparator to thereby select any of the spare memory arrays, a third timing adjustment circuit may be provided between the column address latch circuit and the address comparator. Thus, the optimum operation distribution is further allowed and a cycle time can further be shortened.
In the case of a semiconductor memory device operated based on commands supplied from outside, the value set to the second register is defined as a value for specifying the number of cycles in which the read or write command inputted after the entry of an operation start command is to be inputted in advanced manner. Thus, the clock synchronous memory like the known double data rate synchronous DRAM makes it possible to shorten a cycle time.
Further, the value set to the second register is set based on the state of a terminal to which an external address is inputted when the command supplied from the outside provides instructions for setting thereof to the second register. Thus, the setting thereof to the second register can be carried out without providing any additional external terminal.
Preferably, the timing adjustment circuit comprises at least one delay path having signal delay means, a through path which has no signal delay means and outputs an input signal as it is, and switching means which selects any of the plural paths, for causing the input signal to pass therethrough according to the value set to the second register. Thus, an easy-to-control timing adjustment circuit can be implemented with a relatively simple circuit configuration.
More preferably, master slave-configured latch circuits each operated by the internal control signal are placed in the delay path having the signal delay means of the timing adjustment circuit. It is thus possible to reliably prevent a desired delay from being unavailable due to the sneaking-through of an input signal from an input terminal of the timing adjustment circuit to its output terminal, which is caused by the cue or the like of a clock signal for controlling a circuit.